1. Technical Field
Various embodiments of the present invention relate to semiconductor circuits. In particular, certain embodiments relate to a shift register in a semiconductor apparatus and a synchronization circuit using the same.
2. Related Art
A semiconductor circuit may include a synchronization circuit such as a delay locked loop (DLL) for delay locking or a duty cycle corrector (DCC) for duty cycle correction.
The DLL is used to solve the problem of an increased output data access time due to a delay of an internal clock used in a semiconductor integrated circuit through a clock buffer and a transmission line, which may cause the phase difference between the internal clock and an external clock.
The DCC is used to correct the distortion of the duty cycle of the clock signal.
As semiconductor integrated circuits operate at a higher speed than ever, a delay locking operation and a duct cycle correction operation need to be accurately performed as fast as possible.
FIG. 1 is a block diagram of a synchronization circuit according to the conventional art. As illustrated in FIG. 1, a synchronization circuit 1 according the conventional art includes a coarse delay chain 11, a fine delay chain 12, a driver 13, a replica delay 14, a phase detector 15, a control unit 16, and a shift register 17.
The phase detector 15 detects and outputs the phase difference between an input clock signal CLKIN and a feedback clock signal FBCLK.
Based on the output signal of the phase detector 15, the control unit 16 controls the shift register 17 to perform first delay locking through changing a unit delay time of the coarse delay chain 11.
When the first delay locking is completed, the control unit 16 controls the fine delay chain 12 to perform second delay locking so that it can complete final delay locking and thus output a delay locked clock signal DLLCLK.
Since loop delay inevitably occurs in the conventional art until the feedback clock signal FBCLK is compared with the input clock signal CLKIN and the control unit 16 controls the coarse delay chain 11 and the fine delay chain 12, a substantial amount of time is required to complete the delay locking.